1. Field of the Invention
The present invention relates to a semiconductor memory device incorporating redundancy memory cells.
2. Description of the Related Art
In a semiconductor memory device incorporating redundancy memory cells, in spite of the presence of one or more defective memory cells, the device can be stored by replacing such defective memory cells with their corresponding redundancy memory cells. In this case, addresses (hereinafter, referred to as redundancy addresses) for indicating the defective memory cells are written into a redundancy decoder. Therefore, when an address indicated by address signals coincides with one of the defective addresses, the redundancy decoder accesses the redundancy memory cells, and a normal decoder for accessing the memory cells is disabled. This will be later explained in detail.
In the above-mentioned semiconductor memory device, however, once a redundancy address indicating a defective memory cell is written into the redundancy decoder, it is impossible to access the defective memory cell due to the disabled normal decoder. Therefore, it is impossible to analyze the defective memory cell and confirm whether or not the replacement of the defective memory cell with its redundancy memory cell is correct.